The present invention relates generally to data processors, and more specifically to logic integrated circuits capable of high speed operation.
In prior art data processors wherein a plurality of logic integrated circuits are interconnected in a variety of ways, some of a group of logical paths that extend to a given destination logic gate may go through a greater number of intermediate logic gates than other logical paths of the same group. Such variability can result in pulses arriving at different times at the destination gate due to different delay times, resulting in a shortening of the time "window" in which coincidence must occur between different logical paths. Therefore, the pulse duration at the output of the destination gate is likely to become much narrower than is required if the operating speed, or clock frequency of the processor increases. As a result, information bits to be transmitted to a desired internal flip-flop of the integrated circuit chip are contaminated by noise caused by reflections from impedance mismatches along the logic paths or by crosstalks from external sources. Similar problems occur within a single logic integrated circuit since many logic gates are connected in a variety of combinations and hence input pulses to the output port of the integrated circuit may encounter different delays before arriving at the same output port. Therefore, the pulse duration of the output of the integrated circuit is likely to become considerably short in comparison with the clock interval.